Retrieval of data from a serial bit stream in a physical layer interface (“PHY”) of a networking system, such as a Physical Medium Access (“PMA”) layer of Gigabit Ethernet or PCIe, may be challenging due to a frequency difference between two oscillators, namely an oscillator associated with a transmitter to control the frequency of source data transmitted and an oscillator associated with a receiver used for data acquisition. Due to a relative difference between frequencies of such remote and local oscillators, conventionally local clocking may not be used to directly sample a received serial bit stream.
Instead, encoding may be added to a transmitted serial bit stream to guarantee a minimum toggle rate of such source data, and a clock may thus be recovered from such data transitions, namely clock data recovery (“CDR”), that is frequency locked to such transmitted data stream. While a recovered clock may be used to sample received data to pass such sampled data through buffering to a local clock domain, CDR is conventionally expensive in terms of both power consumption and hardware area used. Overhead associated with CDR conventionally is excessive for use with lower data rates, such as for Gigabit Ethernet (e.g., 1.25 gigabits-per-second (“gbps”)) and PCIe 1.x (e.g., 2.5 gbps). Rather than CDR, in other instances, incrementally phase delayed versions of a local clock have been used to oversample a received data bitstream, and a simple majority rules algorithm has been used to extract data from such oversampled data. However, conventionally cost effective oversampling can be frequency limited due to having to tightly control a phase difference between two clocks. Jitter and phase error on clock signals may significantly contract a system's timing margin.
Hence, it would be desirable and useful to provide data retrieval from a serial bit stream that overcomes one or more of the above-described limitations associated with CDR or oversampling.